Allow setting the boot address as a parameter. If the parameter is not
set, it will fallback to using `OR1200_BOOT_ADR as previously
This makes it easier to set boot address to 0x100 in a testbench to
run with a preloaded ram while being able to use i.e. 0xF0000100 to
use the boot rom when building for a real FPGA.
Changes are for upstream version and orpsocv2 version of or1200
Index: or1200/rtl/verilog/or1200_immu_top.v
===================================================================
--- or1200/rtl/verilog/or1200_immu_top.v (revision 673)
+++ or1200/rtl/verilog/or1200_immu_top.v (working copy)
@@ -75,6 +75,7 @@
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
+parameter boot_adr = `OR1200_BOOT_ADR;
//
// I/O
@@ -148,7 +149,6 @@
wire miss;
wire page_cross;
reg [31:0] icpu_adr_default;
-wire [31:0] icpu_adr_boot;
reg icpu_adr_select;
reg [31:0] icpu_adr_o;
reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
@@ -199,7 +199,7 @@
// selected after boot!
//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P :
// `OR1200_EXCEPT_EPH0_P), 12'h100} ;
- assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
+wire [31:0] icpu_adr_boot = boot_adr;
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
if (icpu_adr_select)
Index: or1200/rtl/verilog/or1200_top.v
===================================================================
--- or1200/rtl/verilog/or1200_top.v (revision 673)
+++ or1200/rtl/verilog/or1200_top.v (working copy)
@@ -97,6 +97,7 @@
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
parameter ppic_ints = `OR1200_PIC_INTS;
+parameter boot_adr = `OR1200_BOOT_ADR;
//
// I/O
@@ -523,7 +524,9 @@
//
// Instantiation of IMMU
//
-or1200_immu_top or1200_immu_top(
+or1200_immu_top
+#(.boot_adr(boot_adr))
+or1200_immu_top(
// Rst and clk
.clk(clk_i),
.rst(rst_i),
Index: orpsocv2/rtl/verilog/or1200/or1200_immu_top.v
===================================================================
--- orpsocv2/rtl/verilog/or1200/or1200_immu_top.v (revision 673)
+++ orpsocv2/rtl/verilog/or1200/or1200_immu_top.v (working copy)
@@ -75,6 +75,7 @@
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
+parameter boot_adr = `OR1200_BOOT_ADR;
//
// I/O
@@ -148,7 +149,6 @@
wire miss;
wire page_cross;
reg [31:0] icpu_adr_default;
-wire [31:0] icpu_adr_boot;
reg icpu_adr_select;
reg [31:0] icpu_adr_o;
reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
@@ -199,7 +199,7 @@
// selected after boot!
//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P :
// `OR1200_EXCEPT_EPH0_P), 12'h100} ;
- assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
+wire [31:0] icpu_adr_boot = boot_adr;
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
if (icpu_adr_select)
Index: orpsocv2/rtl/verilog/or1200/or1200_top.v
===================================================================
--- orpsocv2/rtl/verilog/or1200/or1200_top.v (revision 673)
+++ orpsocv2/rtl/verilog/or1200/or1200_top.v (working copy)
@@ -97,6 +97,7 @@
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
parameter ppic_ints = `OR1200_PIC_INTS;
+parameter boot_adr = `OR1200_BOOT_ADR;
//
// I/O
@@ -523,7 +524,9 @@
//
// Instantiation of IMMU
//
-or1200_immu_top or1200_immu_top(
+or1200_immu_top
+#(.boot_adr(boot_adr))
+or1200_immu_top(
// Rst and clk
.clk(clk_i),
.rst(rst_i),
--
Olof Kindgren
______________________________________________
ORSoC
Website: www.orsoc.se
Email: [email protected]
______________________________________________
FPGA, ASIC, DSP - embedded SoC design
_______________________________________________
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