2012/2/14 Stefan Kristiansson <[email protected]>: > On 02/14/2012 10:56 PM, Olof Kindgren wrote: >> >> Avoids a few compiler warnings >> >> Index: or1200/core/rtl/verilog/or1200_wb_biu.v >> =================================================================== >> --- or1200.orig/core/rtl/verilog/or1200_wb_biu.v 2012-02-14 >> 21:27:56.418564287 +0100 >> +++ or1200/core/rtl/verilog/or1200_wb_biu.v 2012-02-14 >> 21:53:33.894631423 +0100 >> @@ -205,9 +205,9 @@ >> else begin >> // burst counter >> if (wb_fsm_state_cur == wb_fsm_idle) >> - burst_len<= bl[3:0] - 2; >> + burst_len<= bl[3:0] - 4'd2; >> else if (wb_stb_o& wb_ack) >> >> - burst_len<= burst_len - 1; >> + burst_len<= burst_len - 4'd1; >> end >> end >> >> @@ -317,7 +317,7 @@ >> end >> else if (wb_stb_o& wb_ack) begin >> >> if (bl==4) begin >> - wb_adr_o[3:2] <= wb_adr_o[3:2] + 1; >> + wb_adr_o[3:2] <= wb_adr_o[3:2] + 2'd1; >> end >> if (bl==8) begin >> wb_adr_o[4:2] <= wb_adr_o[4:2] + 1; >> >> > > Ack, but shouldn't the last line get the same treatment? > > Stefan
Missed that one, as parameter aw defaults to 32 bits. Not sure if all tools can handle parameterized widths however, so it migh be best to leave that one alone -- Olof Kindgren ______________________________________________ ORSoC Website: www.orsoc.se Email: [email protected] ______________________________________________ FPGA, ASIC, DSP - embedded SoC design _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
