you can also just use " 'b1 " OR " 'h1 " (without specifying any width) example: wb_adr_o[4:2] <= wb_adr_o[4:2] + 'b1;
In verilog 2001, if width is not specified, then automatically the width based on other argument is assumed.. most commercial compilers support this, I think iverilog too supports it.. with regards, pekon
_______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
