Get rid of some compiler warnings
===================================================================
--- or1200.orig/core/rtl/verilog/or1200_wb_biu.v 2012-02-15
00:03:31.926971933 +0100
+++ or1200/core/rtl/verilog/or1200_wb_biu.v 2012-02-15 00:05:09.910976212
+0100
@@ -151,9 +151,6 @@
`ifdef OR1200_WB_RETRY
reg [`OR1200_WB_RETRY-1:0] retry_cnt; // Retry counter
-`else
- wire retry_cnt;
- assign retry_cnt = 1'b0;
`endif
`ifdef OR1200_WB_B3
reg [3:0] burst_len; // burst counter
@@ -415,8 +412,6 @@
assign biu_err_o = (wb_fsm_state_cur == wb_fsm_trans) & wb_err_i
&
wb_stb_o & (wb_err_cnt ~^ biu_err_cnt)
`ifdef OR1200_WB_RETRY
| biu_rty & retry_cnt[`OR1200_WB_RETRY-1];
-`else
- ;
`endif
--
Olof Kindgren
______________________________________________
ORSoC
Website: www.orsoc.se
Email: [email protected]
______________________________________________
FPGA, ASIC, DSP - embedded SoC design
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