Index: or1200/core/rtl/verilog/or1200_ic_top.v =================================================================== --- or1200.orig/core/rtl/verilog/or1200_ic_top.v 2012-02-15 00:08:28.674984890 +0100 +++ or1200/core/rtl/verilog/or1200_ic_top.v 2012-02-15 00:10:46.698990918 +0100 @@ -156,7 +156,6 @@ wire icfsm_first_miss_err; wire icfsm_burst; wire icfsm_tag_we; -reg ic_inv_q;
`ifdef OR1200_BIST // @@ -220,16 +219,6 @@ assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram; // -// Detect falling edge of IC invalidate signal -// -always @(posedge clk or `OR1200_RST_EVENT rst) - if (rst==`OR1200_RST_VALUE) - ic_inv_q <= 1'b0; - else - ic_inv_q <= ic_inv; - - -// // Tag comparison // // During line invalidate, ensure it stays the same -- Olof Kindgren ______________________________________________ ORSoC Website: www.orsoc.se Email: [email protected] ______________________________________________ FPGA, ASIC, DSP - embedded SoC design _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
