On 03/20/2012 04:26 AM, Matthew Hicks wrote:
I brought up issue 1 already, submitted a patch, which was ignored. The cache
and TLBs are not initialized correctly either.
IIRC it was not ignored, there was a discussion about it and the conclusion was
that software
should handle it.
I'd say the same goes for caches and TLBs, you should anyway invalidate the
cache before using it,
so I don't see the problem there?
Stefan
---Matthew Hicks
On Mon, Mar 19, 2012 at 8:35 AM, R. Diez <[email protected]
<mailto:[email protected]>> wrote:
Hi all:
I am trying to run or1ksim's test suite (or at least the test-code-or1k
part) against ORPSoCV2's RTL simulation. So far I hit a couple of minor
issues, namely:
1) or1ksim's test cases assume that all registers are zero on start-up, or
at least that R0 is.
This is probably true for the or1ksim simulator, but on the RTL
simulation, many of the results end up printing a hex value of XXXXXXXX.
The bits in register R0 are probably undefined on start-up. When I added
to the 'basic' test an "l.andi r0,r0,0" at the beginning, it then worked
fine.
This is from file <or1ksim>/testsuite/test-code-or1k/except/except.S :
.section .except,"ax"
.org 0x100
reset_vector:
l.nop
l.nop
l.addi r4,r0,0x0
l.addi r5,r0,0x0
l.addi r6,r0,0x0
l.addi r7,r0,0x0
l.addi r8,r0,0x0
...
Note that the code is not clearing R0 on start-up.
What's the best way forwards? I could reset R0 at the beginning of the
test cases in or1ksim's test suite. Or is there an easiy way to start
ORPSoCV2's RTL simulation with all registers (or at least R0) cleared?
2) The formatting of the results are slightly different, so the 'expect'
scripts fail:
"exit(00000000)" vs "exit(0)"
"report(0x00000009);" vs "report (0x00000009);" (note the extra space)
I guess ORPSoCV2 would be easier to fix, as there are less tests cases to
amend.
Thanks,
R. Diez
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