Here is a link to the patch I submitted: http://lists.openrisc.net/pipermail/openrisc/2011-December/000560.html
I have tested it in hardware (xup-v5) and simulation (ModelSim). ---Matthew Hicks On Tue, Mar 20, 2012 at 3:28 AM, Jeremy Bennett <[email protected] > wrote: > On Mon, 2012-03-19 at 21:26 -0500, Matthew Hicks wrote: > > I brought up issue 1 already, submitted a patch, which was ignored. > > The cache and TLBs are not initialized correctly either. > > Hi Matthew, > > If it was a patch to Or1ksim, apologies - I am the guilty party. Could > you resubmit. I remember us having a long discussion about what this > meant, but I think we all agreed in the end that the spec did not mean > R0 was hard-wired to zero (although an implementation would be free to > do this). > > > Jeremy > -- > Tel: +44 (1590) 610184 > Cell: +44 (7970) 676050 > SkypeID: jeremybennett > Email: [email protected] > Web: www.embecosm.com > > _______________________________________________ > OpenRISC mailing list > [email protected] > http://lists.openrisc.net/listinfo/openrisc >
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