2012/3/27 R. Diez <[email protected]> > Hi Julius: > > In order to run the or1ksim test suite against ORPSoCV2, I wanted to > support these 2 NOP codes: > > NOP_GET_TICKS /* JPB: Get # ticks running */ > NOP_GET_PS /* JPB: Get picosecs/cycle */ > > At least one test case (dhry) uses them. This is the related SystemC code > for NOP_GET_TICKS: > > accessor->setGpr(11, (uint32_t) cycle_count&0xffffffff); > accessor->setGpr(12, (uint32_t) (cycle_count >> 32) & 0xffffffff); > > What is the best way to access that kind of information in ORPSoCV2's > Verilog test bench? Does the test bench maintain the number of clock ticks > somewhere? > > Thanks, > Ruben > ______________________________**_________________ > OpenRISC mailing list > [email protected] > http://lists.openrisc.net/**listinfo/openrisc<http://lists.openrisc.net/listinfo/openrisc> >
You can count the number of rising edges of the wishbone clock, or if you know the clock frequency, you could just get the simulation time (with $time) and divide by the period time -- Olof Kindgren ______________________________________________ ORSoC Website: www.orsoc.se Email: [email protected] ______________________________________________ FPGA, ASIC, DSP - embedded SoC design
_______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
