Hi all:
I have added a basic lint step for ORPSoC V2 to my orbuild system, these
are the results:
------------ Verilator lint begin ------------
/cygdrive/c/Ruben/fpga/orbuild/Builds/build-2012-04-06/VERILATOR-bin/bin/verilator
--lint-only -Wall --error-limit 10000 -Wno-UNUSED -Wno-fatal
-I/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/sim/vlt
-I/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/include
-I/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/bench/verilog/include
-y
/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200
/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_top.v
%Warning-DECLFILENAME:
/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v:323:
Filename 'or1200_fpu_intfloat_conv' does not match MODULE name:
or1200_fpu_intfloat_conv_except
%Warning-DECLFILENAME: Use "/* verilator lint_off DECLFILENAME */" and
lint_on around source to disable this message.
%Warning-UNDRIVEN:
/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_fpu_arith.v:151:
Signal is not driven: mul_24_fract_48
%Warning-UNDRIVEN:
/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_fpu_arith.v:152:
Signal is not driven: mul_24_sign
------------ Verilator lint end ------------
------------ Icarus Verilog lint begin ------------
/cygdrive/c/Ruben/fpga/orbuild/Builds/build-2012-04-06/ICARUS_VERILOG-bin/bin/iverilog
-gno-std-include -Wall -Wno-timescale -g2005 -o /dev/null
-I/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/sim/vlt
-I/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/include
-I/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/bench/verilog/include
-y
/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200
/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_top.v
/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v:147:
warning: Instantiating module or1200_fpu_intfloat_conv_except with
dangling input port 'opb' (floating).
/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v:238:
warning: Instantiating module or1200_fpu_post_norm_intfloat_conv with
dangling input port 'opb_dn' (floating).
------------ Icarus Verilog lint end ------------
If there is any interest I'll add code to lint more of the Verilog sources.
Regards,
Ruben
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