On Wed, Apr 11, 2012 at 4:54 PM, R. Diez <[email protected]> wrote:
> Hi all:
>
> I have added a basic lint step for ORPSoC V2 to my orbuild system, these are
> the results:
>
> ------------ Verilator lint begin ------------
>
> /cygdrive/c/Ruben/fpga/orbuild/Builds/build-2012-04-06/VERILATOR-bin/bin/verilator
> --lint-only -Wall --error-limit 10000 -Wno-UNUSED -Wno-fatal
> -I/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/sim/vlt
> -I/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/include
> -I/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/bench/verilog/include
> -y /cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200
> /cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_top.v
>
> %Warning-DECLFILENAME:
> /cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v:323:
> Filename 'or1200_fpu_intfloat_conv' does not match MODULE name:
> or1200_fpu_intfloat_conv_except
> %Warning-DECLFILENAME: Use "/* verilator lint_off DECLFILENAME */" and
> lint_on around source to disable this message.
> %Warning-UNDRIVEN:
> /cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_fpu_arith.v:151:
> Signal is not driven: mul_24_fract_48
> %Warning-UNDRIVEN:
> /cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_fpu_arith.v:152:
> Signal is not driven: mul_24_sign
These signals come from a commented-out instantiation of a full
multiplier. This has been commented out for a while, and I can't
recall the reason for sticking with serial multiplication for FPU
(something to do with it taking multiple cycles anyway?) but I'm not
sure it's critical to have the choice between serial and full
multiplier there anyway. So they can probably be removed.
Something like:
Index: or1200_fpu_arith.v
===================================================================
--- or1200_fpu_arith.v (revision 794)
+++ or1200_fpu_arith.v (working copy)
@@ -148,8 +148,6 @@
wire [23:0] pre_norm_mul_fracta_24 ;
wire [23:0] pre_norm_mul_fractb_24 ;
wire [47:0] mul_fract_48;
- wire [47:0] mul_24_fract_48;
- wire mul_24_sign;
wire [47:0] serial_mul_fract_48;
wire serial_mul_sign;
wire mul_sign;
@@ -226,19 +224,7 @@
.exp_10_o(pre_norm_mul_exp_10),
.fracta_24_o(pre_norm_mul_fracta_24),
.fractb_24_o(pre_norm_mul_fractb_24));
- /*
- mul_24 i_mul_24
- (
- .clk_i(clk_i) ,
- .fracta_i(pre_norm_mul_fracta_24) ,
- .fractb_i(pre_norm_mul_fractb_24) ,
- .signa_i(s_opa_i[31]),
- .signb_i(s_opb_i[31]),
- .start_i(start_i) ,
- .fract_o(mul_24_fract_48) ,
- .sign_o(mul_24_sign) ,
- .ready_o() );
- */
+
// Serial multiply is default and only one included here
or1200_fpu_mul fpu_mul
(
@@ -253,10 +239,8 @@
.ready_o()
);
- // Serial or parallel multiplier will be chosen depending on constant
- // MUL_SERIAL
- assign mul_fract_48 = MUL_SERIAL ? serial_mul_fract_48 : mul_24_fract_48;
- assign mul_sign = MUL_SERIAL ? serial_mul_sign : mul_24_sign;
+ assign mul_fract_48 = serial_mul_fract_48;
+ assign mul_sign = serial_mul_sign;
or1200_fpu_post_norm_mul fpu_post_norm_mul
(
>
> ------------ Verilator lint end ------------
>
>
> ------------ Icarus Verilog lint begin ------------
>
> /cygdrive/c/Ruben/fpga/orbuild/Builds/build-2012-04-06/ICARUS_VERILOG-bin/bin/iverilog
> -gno-std-include -Wall -Wno-timescale -g2005 -o /dev/null
> -I/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/sim/vlt
> -I/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/include
> -I/cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/bench/verilog/include
> -y /cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200
> /cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_top.v
>
> /cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v:147:
> warning: Instantiating module or1200_fpu_intfloat_conv_except with dangling
> input port 'opb' (floating).
Driving this port to 0 will be fine.
> /cygdrive/c/Ruben/fpga/orbuild/Repositories/ORPSOCV2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v:238:
> warning: Instantiating module or1200_fpu_post_norm_intfloat_conv with
> dangling input port 'opb_dn' (floating).
opb_dn isn't really used, so let's remove it.
Both these fixes are contained in the following patch:
Index: or1200_fpu_intfloat_conv.v
===================================================================
--- or1200_fpu_intfloat_conv.v (revision 794)
+++ or1200_fpu_intfloat_conv.v (working copy)
@@ -147,7 +147,7 @@
or1200_fpu_intfloat_conv_except u0
( .clk(clk),
.opa(opa_r),
- .opb(),
+ .opb(32'd0),
.inf(inf_d),
.ind(ind_d),
.qnan(qnan_d),
@@ -249,7 +249,6 @@
.opa_nan(opa_nan),
.opa_inf(opa_inf),
- .opb_dn(), // Operand B Denormalized
.out(out_d), // Normalized output (un-registered)
.ine(ine_d), // Result Inexact output (un-registered)
.inv(inv_d), // Invalid input for f2i operation
Index: or1200_fpu_post_norm_intfloat_conv.v
===================================================================
--- or1200_fpu_post_norm_intfloat_conv.v (revision 794)
+++ or1200_fpu_post_norm_intfloat_conv.v (working copy)
@@ -40,7 +40,7 @@
module or1200_fpu_post_norm_intfloat_conv
(
clk, fpu_op, opas, sign, rmode, fract_in,
- exp_in, opa_dn, opa_nan, opa_inf, opb_dn, out,
+ exp_in, opa_dn, opa_nan, opa_inf, out,
ine, inv, overflow, underflow, f2i_out_sign
);
input clk;
@@ -50,7 +50,7 @@
input [1:0] rmode;
input [47:0] fract_in;
input [7:0] exp_in;
- input opa_dn, opb_dn;
+ input opa_dn;
input opa_nan, opa_inf;
output [30:0] out;
@@ -74,7 +74,7 @@
wire exp_rnd_adj;
wire [7:0] exp_out_final;
reg [7:0] exp_out_rnd;
- wire op_dn = opa_dn | opb_dn;
+ wire op_dn = opa_dn;
wire op_mul = fpu_op[2:0]==3'b010;
wire op_div = fpu_op[2:0]==3'b011;
wire op_i2f = fpu_op[2:0]==3'b100;
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