Hi OpenRISC gurus:I need a new "l.halt" or "l.sleep" instruction to make my OR10 CPU stop using the Wishbone bus and wait for the next interrupt.
Can anybody suggest a suitable opcode? Is this something we may want to add to the specification? Or did I miss such an instruction?
Thanks, rdiez _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
