On Sat, Oct 6, 2012 at 4:59 PM, R. Diez <[email protected]> wrote: > Hi OpenRISC gurus: > > I need a new "l.halt" or "l.sleep" instruction to make my OR10 CPU stop > using the Wishbone bus and wait for the next interrupt. > > Can anybody suggest a suitable opcode? Is this something we may want to add > to the specification? Or did I miss such an instruction?
Hi Ruben This is exactly something I was pondering this week myself. I really think we should add such an instruction, and make it possible for the processor to continue execution on exception (timer or interrupt, basically.) Feel free to propose a new instruction on the page I linked to in my previous answer: http://opencores.org/or1k/Architecture_Specification We'll have a session at next weekend's OpenRISC project meeting in Stockholm to discuss all of the things on that page, so it'd be great if we had a proposal for a sleep or halt instruction. Thanks Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
