On Sat, Oct 6, 2012 at 4:56 PM, R. Diez <[email protected]> wrote: > Hi OpenRISC gurus: > > I've been adding a JTAG Debug Unit to my OR10 CPU, and I realised that the > l.trap argument actually gets ignored by the current processor > implementations, doesn't it? > > This is from the "OpenRISC 1000 Architecture Manual": > > "Execution of trap instruction results in the trap exception if specified > bit in SR is set." > > GDB inserts an "l.trap 1" instruction if the remote gdbserver doesn't > support setting breakpoints itself. SR bit 1 is the "Tick Timer Exception > Enabled" flag, which has nothing to do with debug breakpoints. I guess we > could use the SR FO bit (Fixed One), but I wonder whether the FPGA extra > logic is worth it. Shouldn't we just remove that requirement from the > specification? I mean, the CPU should always ignore the l.trap argument > (like current implementations seem to do) and always raise the exception (or > transfer control to the Debug Interface if enabled).
I do think we should remove this condition on the l.trap instruction executing, and it's already proposed: http://opencores.org/or1k/Architecture_Specification#l.trap_condition > > By the way, the "OpenRISC 1000 Architecture Manual" I have (from > http://opencores.org/ocsvn/openrisc/openrisc/trunk/docs) is dated from 2006, > is there a newer version yet? There is a newer "draft" but the whole thing is in a bit of a mess at the moment. http://opencores.org/ocsvn/openrisc/openrisc/trunk/docs/openrisc_arch_draft.odt Cheers Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
