On Mon, Oct 8, 2012 at 9:46 PM, Franck Jullien <[email protected]> wrote: > Hi, > > As I was investigating on an IC problem on my Altera board, I found a > wrong behavior (that's what I think) on the wb_cyc_o output from the > or1200_wb_biu. > At some point, when the biu_cyc_i to the biu is desaserted, the biu > fsm is still waiting for an ack from the wishbone and the biu_cyc_i > desasertion is not followed to the wb side. >
Hi Franck, Looks good I think. If the ORPSoC regression suite passes with this change then I reckon it's fine. Although, can you confirm this doesn't result in any invalid behaviour by the CPU's instruction master on the Wishbone bus? (We really need some checkers....) Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
