On Mon, 2012-10-08 at 22:46 +0200, Franck Jullien wrote: > Hi, > > As I was investigating on an IC problem on my Altera board, I found a > wrong behavior (that's what I think) on the wb_cyc_o output from the > or1200_wb_biu. > At some point, when the biu_cyc_i to the biu is desaserted, the biu > fsm is still waiting for an ack from the wishbone and the biu_cyc_i > desasertion is not followed to the wb side. > > Attached patch fix this.
Hi, just for curiosity as we recently faced the same "issue". Doesn't de-asserting the cycle and strobe without waiting for the ack break the protocol? We had the case that a second level cache was connected at the BIU and because of internal changes to the L1 cache the BIU incorrectly aborted a transaction. As the fetching at L2 took kind of long the corresponding ack was then incorrectly attributed to the next transaction of the BIU. From what I see, the Bus Master can not easily abort a bus transaction or am I wrong? Bye, Stefan -- Stefan Wallentowitz _/ _/_/_/ _/_/_/ Institute for Integrated Systems (LIS) _/ _/ _/ Technische Universität München _/ _/ _/_/ D-80290 München _/ _/ _/ fon +49 89 289 22963 _/_/_/_/ _/_/_/ _/_/_/ [email protected] http://www.lis.ei.tum.de
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