2012/10/10 Stefan Wallentowitz <[email protected]>: > >> I would say that too. From what I known, de-asserting the cycle and >> strobe is the only way for a master to abort a bus transaction (but >> I'm not a wb expert). >> So I guess it's ok.... >> >> Franck. > > Wishbone is quite clear on this: "As shown in Figure 3-2, the MASTER > asserts [STB_O] when it is ready to transfer data. [STB_O] remains > asserted until the SLAVE asserts one of the cycle terminating signals > [ACK_I], [ERR_I] or [RTY_I]." (Wishbone B3, page 41). > > There is no abortion of bus transfers from the master side. An abortion > will result in unexpected behavior in the bus implementation with longer > delays of the slave i would say. That might brake other systems. > > I think the problem needs to be fixed on the IC or genpc side, or the > BIU needs an extra state where it waits for the cycle termination. I > will have a look at the code and come back to you later. > > Bye, > Stefan > > -- > Stefan Wallentowitz _/ _/_/_/ _/_/_/ > Institute for Integrated Systems (LIS) _/ _/ _/ > Technische Universität München _/ _/ _/_/ > D-80290 München _/ _/ _/ > fon +49 89 289 22963 _/_/_/_/ _/_/_/ _/_/_/ > > [email protected] http://www.lis.ei.tum.de
So the question is: is there any problem at all in the waveform attached in my original post (the one on the top) ? May be that it should stay like it is. The biu_cyc_i low transition we are seeing is due to the page_cross signal in the immu. Franck. _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
