On Wed, Oct 17, 2012 at 12:51 PM, Olof Kindgren <[email protected]> wrote: > 2012/10/17 Vaidya Bhaumik Vidyutkumar <[email protected]>: >> >> Hii , >> >> We as a group are working on ASIC SOC with openrisc 1200 as its central >> processor. I know it has Wishbone interface but we want to use AMBA AHB as >> system bus so is it possible to use it and what modification do we need to >> make to achieve this ? >> >> Thanks and Regards, >> Bhaumik >> >> _______________________________________________ >> Openrisc mailing list >> [email protected] >> http://lists.opencores.org/listinfo/openrisc > > Hi Bhaumik, > > There are two ways to do this. Either you make the changes to the > or1200 itself, or create a stand-alone Wishbone-AHB bridge. Making the > necessary changes to or1200 can be a bit tricky, since the wishbone > interface is very integrated in the core.
I actually think the opposite. Integrating the bridge wouldn't be hard, as the internal interface in the OR1200 isn't too Wishbone specific (it's reminiscent of early Wishbone stuff, with a consecutive burst-like signal). I reckon you could do enough verification in a relatively short amount of time to convince yourself that it's OK. I'd actually like to see AMBA stuff put in the mor1kx, too. If you're interested in using a newer OR1K-processor implementation I'd encourage you to look at the mor1kx project: http://github.com/juliusbaxter/mor1kx Cheers Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
