Hi all:
While testing my OR10 CPU with Verilator, I realised that the Wishbone
bus hangs when the CPU tries to access an invalid address like 0xF0000000.
I took a quick look at the "Xess Traffic Cop" Wishbone switch used by
MinSoC and ORPSoC, which I'm using too, and the problem is probably that
there is no device (RAM or peripheral) that handles the address range
starting with F0.
It does not seem like this Wishbone switch generates a bus error itself
when a master tries to access an address not covered by any of the
attached slaves.
I would like to add some error-detection logic for this case. If saving
FPGA resources is more important than detecting invalid addresses, such
a check could be made optional.
The trouble is, I don't understand how the Wishbone switch works.
Is anybody familiar enough with the implementation?
Thanks,
rdiez
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