2012/11/7 Franck Jullien <[email protected]> > 2012/11/7 Marek Czerski <[email protected]>: > > > > > > 2012/11/5 Marek Czerski <[email protected]> > >>> > >>> > >>> > >>> I have a fix ready. I works on VPI simulation. I don't know if it's a > >>> good or the right way to fix this but at least it seems to work.... > >>> If someone could give it a try on an hardware platform that would be > >>> great (because I'm not home this week end). > >>> > >>> Franck. > >> > >> > >> The fix works well on hardware with adv_debug_sys and adv_debug_bridge. > >> But why it works without this fix with adv_debug_sys and OpenOCD ? And > the > >> problem with OpenOCD and single-stepping through jumps instructions > still > >> exists. I also noticed that removing software breakpoints don't work > when > >> instruction cache is enabled. I think it is reasonable to flush cache > after > >> inserting or removing software breakpoints but the jtag software is not > >> doing that. > >> > >> > >> -- > >> mgr inż. Marek Czerski > >> +48 696 842 686 > >> > > > > OK, after a little bit of struggle I finaly found some dirty fix for > OpenOCD > > and single-stepping through branch instruction. I found out that, while > > stepping through l.jal instruction, link register is updated correctly, > but > > next step through l.nop doesn't update npc register in the right way > (npc is > > set to the next address after l.nop and not to the jump address). It > turn > > out that if register context is not restored during single stepping mode > > (or1k_resume_or_step in or1k.c with step argument set to 1) the npc > register > > is updated correctly. > > I also notticed that the BT bit in DMR1 register is not set during > > single-stepping. Is it correct ? > > I prepared a patch, but i'm not convinced that this is the correct > solution, > > so maybe someone who knows OpenOCD better can check it. I also added > cache > > invalidation during addition and removal of software breakpoints so it is > > now working correctly with cache enabled. > > > > -- > > mgr inż. Marek Czerski > > +48 696 842 686 > > > > It doesn't work for me.... > > How did you debug your setup (are you only hacking openOCD or you are > using signaltap/chipscope) ? > > The cache invalidation is good fore sure. > > Franck. >
I'm not using signal tap . I use OpenOCD with adv_debug_sys and altera virtual jtag. FPGA is programmed with orpsoc project from git:// openrisc.net/stefan/orpsoc (latest release from master branch patched with the patch You sent). Be sure to apply patch, otherwise instructions after breakpoint won't execute. -- mgr inż. Marek Czerski +48 696 842 686
_______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
