Hi all I've updated the architecture specification, adding things we agreed upon at the project meeting.
http://opencores.org/or1k/Talk:Architecture_Specification#Discussion_at_OpenRISC_Project_Meeting.2C_October.2C_2012 I've not stuck to the letter of what was agreed upon, differing only in things like SPR register numbering, and adding new register-presence bits in the CPUCFGR, all pretty obvious things which needed to go along with the updates. Find the draft PDF file here: https://www.dropbox.com/s/jsavdj0zve3i7v0/openrisc-arch-1.0-draft.pdf Things I haven't addressed are instruction classes (we still don't have a consensus on this, probably never will, but need to take the plunge at some point, just not tonight) and features we haven't completely fleshed out, like multi-processor synchronisation instructions like load-linked store conditional. The discussion continues here on the lists and on the wiki: http://opencores.org/or1k/Architecture_Specification - please come and contribute so we can sort it out ASAP. However, we now have proper version tracking for implementations and the document. It should be trivial to add new features, correct things, and know what implementations correspond to what generation of the spec. I'd like to push this to the SVN master soon, so we can get on with implementations which use these new architectural features. _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
