Hi, I ported GDB to the or1k toolchain. It is now GDB 7.5.
I you want to test it, it's here: https://github.com/Franck79/or1k-src/commit/prepare_patch I basically copied or32-tdep files from GDB 7.2.... I replaced all or32 names with or1k. This port support or1k and or1knd target. The default target is or1k. To change this, use: (gdb) set architecture or1knd The target architecture is assumed to be or1knd (the no delay slot target has not been tested). This are the only (functional) changes: + Notes on the GDB 7.5 version + ============================ + + This version is just an upgrade of the previous port. It does use CGEN + for instruction lookup in or1k_single_step_through_delay as the new toolchain + is CGEN based. + + This version is compatible with or1knd target (no delay slot version of the + toolchain). A check in bfd_arch_info mach value is done (bfd_mach_or1k or + bfd_mach_or1knd) to choose if or1k_single_step_through_delay must be + implemented. + ----> Please comment, correct this. @@ -541,20 +573,22 @@ /*--------------------------------------------------------------------------*/ static int -or32_single_step_through_delay( struct gdbarch *gdbarch, +or1k_single_step_through_delay( struct gdbarch *gdbarch, struct frame_info *this_frame ) { ........ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ........ - /* Decode the previous instruction to see if it was a branch or a jump, and - hence we are in a delay slot. */ - index = insn_decode (or32_fetch_instruction (gdbarch, ppc)); - return or32_opcodes[index].flags & OR32_IF_DELAY; ----> Don't use the automata thing anymore + insns = cgen_lookup_insn (tdep->gdb_cgen_cpu_desc, + NULL, + or1k_fetch_instruction (gdbarch, ppc), + NULL, + 32, + &tmp_fields, + 0); + + /* TODO: we should add a delay slot flag to the CGEN_INSN and remove + * this hard coded test. */ ----> Should we do that ? (other arch are doing it like I did here). + return ((CGEN_INSN_NUM(insns) == OR1K_INSN_L_J) || + (CGEN_INSN_NUM(insns) == OR1K_INSN_L_JAL) || + (CGEN_INSN_NUM(insns) == OR1K_INSN_L_JR) || + (CGEN_INSN_NUM(insns) == OR1K_INSN_L_JALR) || + (CGEN_INSN_NUM(insns) == OR1K_INSN_L_BNF) || + (CGEN_INSN_NUM(insns) == OR1K_INSN_L_BF)); ..... - switch (gdbarch_byte_order (gdbarch)) - { - case BFD_ENDIAN_BIG: - set_gdbarch_print_insn (gdbarch, print_insn_big_or32); - break; - - case BFD_ENDIAN_LITTLE: - set_gdbarch_print_insn (gdbarch, print_insn_little_or32); - break; - case BFD_ENDIAN_UNKNOWN: - error ("or32_gdbarch_init: Unknown endianness"); - break; - } + set_gdbarch_print_insn (gdbarch, print_insn_or1k); ----> print_insn_or1k is now endian aware ..... + /* Get a CGEN CPU descriptor for this architecture. */ + { + + const char *mach_name = binfo->printable_name; + enum cgen_endian endian = (info.byte_order == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + + tdep->gdb_cgen_cpu_desc = or1k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); + + or1k_cgen_init_asm (tdep->gdb_cgen_cpu_desc); + } + + /* If this mach as delay slot */ + if (binfo->mach == bfd_mach_or1k) + { + set_gdbarch_single_step_through_delay + (gdbarch, or1k_single_step_through_delay); + } ----> Don't use the automata thing anymore ...... - /* Initialize the automata for the assembler */ - build_automata(); ----> Don't use the automata thing anymore ....... +static const struct frame_unwind or1k_frame_unwind = { .type = NORMAL_FRAME, - .this_id = or32_frame_this_id, - .prev_register = or32_frame_prev_register, + .stop_reason = default_frame_unwind_stop_reason, + .this_id = or1k_frame_this_id, + .prev_register = or1k_frame_prev_register, .unwind_data = NULL, .sniffer = default_frame_sniffer, .dealloc_cache = NULL, ----> there is a new handler, stop_reason. Assign default handler to it. Franck. _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
