On 15/11/13 08:39, Olof Kindgren wrote: > Hi Jose, > > This would be really useful as it's a piece of functionality that is > currently missing in ORPSoCv3, so don't hesitate to ask for help if you > get stuck, and come see us at #openrisc on irc.freenode.net > <http://irc.freenode.net> where you can find most of the active developers.
Hi Jose, I didn't see your original post. You might find the Embecosm Application Note 5: "Using JTAG with SystemC: Implementation of a Cycle Accurate Interface" useful. You can download it from http://www.embecosm.com/resources/appnotes/#EAN5. This uses ORPSoC and Verilator in its reference example in Chapter 4, although it is based on ORPSoCv1. You may also find Application Note 7: "Integrating the GNU Debugger with Cycle Accurate Models: A Case Study using a Verilator SystemC Model of the OpenRISC 1000" useful. You can download it from http://www.embecosm.com/resources/appnotes/#EAN7. > We had something similar in ORPSoCv2, but with a different approach. > Instead of connecting with OpenOCD to the verilated model, we had a > complete GDB server in the sysC model and connected directly with GDB. > The big drawback of that approach was that we didn't maintain the GDB > server properly, so after some time it didn't have the same > functionality as you would get from connecting to a real board with > OpenOCD. I think that your best starting point would be to look at both > jtag_vpi.c/v and also see if you can rip out the JTAG pin driving parts > from the old ORPSoCv2 JTAG model. You can find the old code here: > http://opencores.org/websvn,listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F#path_openrisc_trunk_orpsocv2_bench_sysc_src_ > > One problem that might hit you is that generating SystemC models with > verilator is untested (and probably unsupported atm). The reason for > that is that I didn't strictly need SystemC for the test benches that I > did, so I configured verilator to generate plan C++ instead to avoid > having the SystemC dependencies. Having SysC support will probably be > useful anyway, so I'll start looking into adding support for that when > I have time. Not sure quite what you mean by this. Verilator absolutely supports SystemC, including SystemC 2.3, and has done for years. The example in the application note above uses a SystemC Verilator model of ORPSoC. I haven't tried with ORPSoCv3, but I can't think of any reason why Verilator wouldn't work out of the box. HTH, Jeremy > Regards, > Olof > > > > > 2013/11/15 Jose Teixeira de Sousa <[email protected] <mailto:[email protected]>> > > Hi, > > I am looking to find or build a sort of JTAG server to be placed in > a SysC model to be run by Verilator. > > This server would accept connections from an OpenOCD client driver, > just as if it were a board. > > Internally to the SysC model this component would drive the JTAG > pins of OrpSoc. > > Please: > > 1) has anybody worked on such thing that could provide a pointer? > > 2) I was thinking to start from jtag_vpi.c(.v) and go from there. > > 3) I find this useful. Could anybody make any comments on the above? > > Thanks, > > Jose > > > > > > -- > Jose T. de Sousa, PhD > Office: +351 213 100 213 <tel:%2B351%20213%20100%20213> > R. Alves Redol 9 > 1000-029 Lisboa > Portugal > > > > > _______________________________________________ > OpenRISC mailing list > [email protected] > http://lists.openrisc.net/listinfo/openrisc > -- Tel: +44 (1590) 610184 Cell: +44 (7970) 676050 SkypeId: jeremybennett Email: [email protected] Web: www.embecosm.com Twitter: @embecosm _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
