Hi Olof, all, I have a first drop of the SystemC verilator testbench. Please see https://github.com/jjts/orpsoc-cores and https://github.com/jjts/orpsoc-3.1
I started off from jtag_vpi.c/v and running the (slow) icarus simulator and then I wrote them in SystemC/C++. So now communicating with the Verilator model is similar to communicating to icarus or De0_nano. I use openocd with telnet or gdb to connect to it. Some observations: 1) With openocd and telnet I did not detect abnormal behavior so far. 2) with the stable toolchain I get the following gdb mesg : "some target registers not supported by current architecture", or something alike. with the recent toolchain I don't. I need to set remotetimeout 15 in order for it to load the program Running and breakpoints work. "step" and "next" have funny behavior - I wonder why. Breaking at printf and then doing "next" causes it to stop somewhere in printf rather than jumping over and stopping on the next command. I don't remember seeing this on the board and need to chack again... Any clues? Thanks Jose 2013/11/15 Olof Kindgren <[email protected]> > Hi Jose, > > This would be really useful as it's a piece of functionality that is > currently missing in ORPSoCv3, so don't hesitate to ask for help if you get > stuck, and come see us at #openrisc on irc.freenode.net where you can > find most of the active developers. > > We had something similar in ORPSoCv2, but with a different approach. > Instead of connecting with OpenOCD to the verilated model, we had a > complete GDB server in the sysC model and connected directly with GDB. The > big drawback of that approach was that we didn't maintain the GDB server > properly, so after some time it didn't have the same functionality as you > would get from connecting to a real board with OpenOCD. I think that your > best starting point would be to look at both jtag_vpi.c/v and also see if > you can rip out the JTAG pin driving parts from the old ORPSoCv2 JTAG > model. You can find the old code here: > http://opencores.org/websvn,listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F#path_openrisc_trunk_orpsocv2_bench_sysc_src_ > > One problem that might hit you is that generating SystemC models with > verilator is untested (and probably unsupported atm). The reason for that > is that I didn't strictly need SystemC for the test benches that I did, so > I configured verilator to generate plan C++ instead to avoid having the > SystemC dependencies. Having SysC support will probably be useful anyway, > so I'll start looking into adding support for that when I have time. > > Regards, > Olof > > > > > 2013/11/15 Jose Teixeira de Sousa <[email protected]> > >> Hi, >> >> I am looking to find or build a sort of JTAG server to be placed in a >> SysC model to be run by Verilator. >> >> This server would accept connections from an OpenOCD client driver, just >> as if it were a board. >> >> Internally to the SysC model this component would drive the JTAG pins of >> OrpSoc. >> >> Please: >> >> 1) has anybody worked on such thing that could provide a pointer? >> >> 2) I was thinking to start from jtag_vpi.c(.v) and go from there. >> >> 3) I find this useful. Could anybody make any comments on the above? >> >> Thanks, >> >> Jose >> >> >> >> >> >> -- >> Jose T. de Sousa, PhD >> Office: +351 213 100 213 >> R. Alves Redol 9 >> 1000-029 Lisboa >> Portugal >> > > -- Jose T. de Sousa, PhD Office: +351 213 100 213 R. Alves Redol 9 1000-029 Lisboa Portugal
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