Hi, I'm using the Wishbone DDR2 controller for the Atlys in another opensource project. It'll have to do only 8 beat (and possibly 4 beat) wrapping burst transfers. I saw the version in Stefan's repository http://git.openrisc.net/cgit.cgi/stefan/orpsoc/tree/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2is quite old and doesn't support the wrapping bursts I need, but is tested and works. The version in the official orpsocv2 SVN repository supports those modes, but is it tested? Does it work reliably?
Is there any quirk my logic needs to cope with? -- Francesco Gugliuzza B.Sc. in Computer Engineering HackLabProject.org Administrator ilpuntotecnicoeadsl.com Administrator E-mail: [email protected]
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