On Mon, Mar 3, 2014 at 4:36 PM, Francesco Gugliuzza <[email protected]> wrote: > I'm using the Wishbone DDR2 controller for the Atlys in another opensource > project. It'll have to do only 8 beat (and possibly 4 beat) wrapping burst > transfers. > I saw the version in Stefan's repository > http://git.openrisc.net/cgit.cgi/stefan/orpsoc/tree/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2 > is quite old and doesn't support the wrapping bursts I need, but is tested > and works.
It supports wrapping bursts, but it depends on your definition of "support". It can handle wrapping burst transfers issued by a wishbone master just fine, but since the Xilinx DDR2 memory controller doesn't support (iirc) fetching data from memory in that way there's no way to make the wrapping bursts really efficient. > The version in the official orpsocv2 SVN repository supports > those modes, but is it tested? Does it work reliably? > FWIW, this is even older and doesn't have any "better" support for wrapping bursts. Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
