Hi Stefan, I'd say this looks good.
On Thu, Apr 10, 2014 at 4:09 PM, Stefan Kristiansson < [email protected]> wrote: > - The granularity of the link is a word. > (I'm certainly open for discussions on this one, e.g. a cacheline could > make > sense too) > I think a single word is fine. Doing the whole cacheline would be more complex, wouldn't it? Plus if the whole cache line was linked it would mean code that uses atomic instructions needs to know the cache line size, which might be annoying. > > - The result (1 for success and 0 for fail) of the store conditional is > stored > in the source register of the l.swa instruction. > I.e. 'rB' in 'l.swa I(rA), rB'. > (I was in a split mind between choosing the flag bit, the carry bit or > the l.swa source register. The reason I choose the register is because > the > flag is easily a critical path in the rtl implementations, the carry bit > requires l.addc which isn't always included (despite being a mandatory > instruction)) > The only nit I really have is that writing the result to a register doesn't fit the rest of the ISA. Is the F flag timing path on the mork1x tighter than the forwarding path needed to pass the result of l.swa to earlier pipeline stages would be? Because if the result can't be forwarded, there would have to be a pipeline bubble. If either solution causes a pipeline bubble, I'd prefer just to put the result in the F flag. -Pete
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