On Thu, Apr 10, 2014 at 11:47 PM, Peter Gavin <[email protected]> wrote: > On Thu, Apr 10, 2014 at 4:09 PM, Stefan Kristiansson > <[email protected]> wrote: >> - The result (1 for success and 0 for fail) of the store conditional is >> stored >> in the source register of the l.swa instruction. >> I.e. 'rB' in 'l.swa I(rA), rB'. >> (I was in a split mind between choosing the flag bit, the carry bit or >> the l.swa source register. The reason I choose the register is because >> the >> flag is easily a critical path in the rtl implementations, the carry bit >> requires l.addc which isn't always included (despite being a mandatory >> instruction)) > > > The only nit I really have is that writing the result to a register doesn't > fit the rest of the ISA. Is the F flag timing path on the mork1x tighter > than the forwarding path needed to pass the result of l.swa to earlier > pipeline stages would be? Because if the result can't be forwarded, there > would have to be a pipeline bubble. If either solution causes a pipeline > bubble, I'd prefer just to put the result in the F flag. >
Hmm, yeah, good point. I guess the only real way to find out is to try, I'll experiment with both solutions. I agree that the F flag would be more elegant from an ISA point of view, and it also have the nice property that a rmw loop would be tighter: 1: l.lwa r3, 0(r4) l.addi r3,r3,1 l.swa 0(r4), r3 l.bf 1b l.nop Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
