Hi, > After some more in-depth testing, I found one small issue, for which I > have already pushed a fix for: > https://github.com/openrisc/mor1kx/commit/7db7a341f9886851fb18d6c4a1a0b00de7016f24 Perfect, thank you! > As a slightly related note - in retro-perspective, I think it was a > mistake to keep all the ways in *one* tag memory. > I did that as a way to more efficiently use the block ram in FPGAs, > but in the end, I think the trade-offs are to costly. > The split-up of the tag memory data when it's read and written that > you did in those commits have already made it easier to make a > transition for that. At least Synplify (did not try other synthesis) still uses Block RAM rather efficiently, but maybe it makes more sense to split it.
Another thing along those lines: I read that one way to cope with the issues of VIPT caches is to store tag plus index. Should we consider this? At the moment we set the cache size to page size to avoid the issues. Bye, Stefan
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