On Wed, Apr 16, 2014 at 4:23 PM, Stefan Wallentowitz <[email protected]> wrote: > On 04/16/2014 02:54 PM, Stefan Kristiansson wrote: >> Can't you use per-cpu register save-slots in shared memory? > Yes, of course, but you will always need two "clean" registers.
Why two? I just did it with only one.. You can get away without using 0x0-0x100 if you stay within addresses that are within the reach of 'I' in l.sw I(rB), rA too. >> I'm personally not very fond of the other alternatives, that's why I'm >> being difficult here. >> In my opinion it would even be more preferable to reserve another GPR >> for kernel/OS use than the other alternatives. > I understand your reservation here, but the hack is extremely dirty and > a clean solution much more desireable. Just defining r30 and r31 (or any > other) to be reserved for exception handling is a rather hard step from > an ABI point of view, isn't it? > Yeah, I agree that pinning down registers are neither a desirable path. But, I also don't think ad-hoc hardware hacks is any more desirable than SW ones. If we're going to add shadow registers, then we need to either properly redefine the current "fast context switch" definition in the arch manual or somehow use that. > Meanwhile, I will continue and simply use ISR0 and ISR1 for this > purpose. In mor1kx they currently serve exactly as what I need.. > Ah, I forgot to mention that. I think they are HW implementation specific, so you should be able to any custom needs you have. Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
