Update on this, I've added 'Atomicity' chapter and the l.lwa and l.swa instructions to the arch spec, with the things that we discussed in this thread. The updated arch spec can be found here for review: https://www.dropbox.com/s/yqyfelu2yrutzwt/openrisc-arch-1.1-rev0.pdf or as .odt: https://www.dropbox.com/s/bzez95ix1cl0g7g/openrisc-arch-1.1-rev0.odt
For convenience, this is the added text in 'plain text' (copied straight from the .odt): "7.3 Atomicity A memory access is atomic if it is always performed in its entirety with no visible fragmentation. Atomic memory accesses are specifically required to implement software semaphores and other shared structures in systems where two different processes on the same processor, or two different processors in a multiprocessor environment, access the same memory location with intent to modify it. The OpenRISC 1000 architecture provides two dedicated instructions that together perform an atomic read-modify-write operation. l.lwa rD, I(rA) l.swa I(rA), rB Instruction l.lwa loads single word from memory, creating a reservation for a subsequent conditional store operation. A special register, invisible to the programmer, is used to hold the address of the memory location, which is used in the atomic read-modify-write operation. The reservation for a subsequent l.swa is cancelled if another store to the same memory location occur, another master writes the same memory location (snoop hit), another l.swa (to any memory location) is executed, another l.lwa is executed or a context switch (exception) occur. If a reservation is still valid when the corresponding l.swa is executed, l.swa stores general-purpose register rB into the memory and SR[F] is set. If the reservation was cancelled, l.swa does not perform the store to memory and SR[F] is cleared." "l.lwa rD,I(rA) Description: The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The single word in memory addressed by EA is loaded into the low-order 32 bits of general-purpose register rD. High-order bits of general-purpose register rD are replaced with zero. Two internal registers are set, one 1-bit flag register that will be referred to as atomic_reserve and a 32/64-bit address register that will be referred to as atomic_address. The atomic_address register will be set to EA. 32-bit Implementation: EA ← exts(Immediate) + rA[31:0] rD[31:0] ← (EA)[31:0] atomic_reserve ← 1 atomic_address ← EA 64-bit Implementation: EA ← exts(Immediate) + rA[63:0] rD[31:0] ← (EA)[31:0] rD[63:32] ← 0 atomic_reserve ← 1 atomic_address ← EA Exceptions: TLB miss Page fault Bus error Alignment" "l.swa I(rA),rB Description: The offset is sign-extended and added to the contents of general-purpose register rA. The sum represents an effective address. The low-order 32 bits of general-purpose register rB are conditionally stored to memory location addressed by EA. The 'atomic' condition relies on that an atomic reserve to EA is still intact (i.e. that the atomic_reserve internal register mentioned in the l.lwa instruction is still set and the internal atomic_address register matches EA). 32-bit Implementation: EA ← exts(Immediate) + rA[31:0] if (atomic) (EA)[31:0] ← rB[31:0] SR[F] ← atomic 64-bit Implementation: EA ← exts(Immediate) + rA[63:0] if (atomic) (EA)[31:0] ← rB[31:0] SR[F] ← atomic Exceptions: TLB miss Page fault Bus error Alignment" _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
