Oliver Yang wrote:
Hi All,
I found the Solaris x86 has the real implementation for store
instruction ordering,
x64,
ENTRY(membar_producer)
sfence
ret
SET_SIZE(membar_producer)
x32,
ENTRY(membar_producer)
.globl _patch_sfence_ret
_patch_sfence_ret: /* c.f. membar #StoreStore */
lock
xorl $0, (%esp)
ret
SET_SIZE(membar_producer)
But I was told that x86 architecture always enforces ordered writes.
I realized that above statement is not true, it seems that winchip CPU
from VIA support weak ordering mode.
If that is true, should we have an empty membar_producer routine?
I think we should have the dummy routine for Intel/AMD cpu, since the
extra sfence or lock instructions on SMP platform are expensive.
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