Oliver Yang wrote:
Oliver Yang wrote:
Hi All,
I found the Solaris x86 has the real implementation for store
instruction ordering,
x64,
ENTRY(membar_producer)
sfence
ret
SET_SIZE(membar_producer)
x32,
ENTRY(membar_producer)
.globl _patch_sfence_ret
_patch_sfence_ret: /* c.f. membar #StoreStore */
lock
xorl $0, (%esp)
ret
SET_SIZE(membar_producer)
But I was told that x86 architecture always enforces ordered writes.
I realized that above statement is not true, it seems that winchip CPU
from VIA support weak ordering mode.
Please ignore my proposal,
I found AMD64 also has Write-Combing memory which supports out of order
store, so I think current implementation is OK.
_______________________________________________
opensolaris-code mailing list
opensolaris-code@opensolaris.org
http://mail.opensolaris.org/mailman/listinfo/opensolaris-code
