> after BFU of snv_68 :
>
> module /platform/i86pc/kernel//unix: text at [0xfe800000, 0xfe8d4a8b] data at
> 0xfec00000
> module /kernel/genunix: text at [0xfe8d4a90, 0xfead88ff] data at 0xfec4cdc0
>
> panic[cpu0]/thread=fec1f2e0: assertion failed: ((((l2cache_assoc ?
> (l2cache_sz / l2cache_assoc) : 0x1000)) & (((l2cache_assoc ? (l2cache_sz /
> l2cache_assoc) : 0x1000)) - 1)) == 0), file
>
> fec382d0 genunix:assfail+5a (fe8c936c, fe8c95ec,)
> fec38300 unix:page_coloring_init+35a (20000, 40, a)
> fec38358 unix:startup_memlist+3f5 (fec38384,fe954503,)
> fec38360 unix:startup+1c (fe800010, fec34128,)
> fec38384 genunix:main+5b ()
Can you try to boot with kmdb enabled (kernel boot option: "-k")
and print the values for "l2cache_sz" and "l2cache_assoc", when it
stops at the panic / failed assertion ?
l2cache_sz::print
l2cache_assoc::print
> cpu0: x86 (CentaurHauls 6A9 family 6 model 10 step 9 clock 1200 MHz)
> cpu0: VIA Esther processor 1200MHz
Could be missing / broken or incomplete VIA/CentaurHauls x86 cpu support:
http://src.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/uts/i86pc/os/startup.c#1000
1000 /*
1001 * determine l2 cache info and memory size for page coloring
1002 */
1003 (void) getl2cacheinfo(CPU,
1004 &l2cache_sz, &l2cache_linesz, &l2cache_assoc);
1005 pagecolor_memsz =
1006 page_coloring_init(l2cache_sz, l2cache_linesz,
l2cache_assoc);
In getl2cacheinfo(), I see support for Intel, AMD and Cyrix, but no support
for VIA / CentaurHauls cpus?
http://src.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/uts/i86pc/os/cpuid.c#3300
3300 int
3301 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc)
3302 {
3303 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3304 struct l2info __l2info, *l2i = &__l2info;
3305
3306 l2i->l2i_csz = csz;
3307 l2i->l2i_lsz = lsz;
3308 l2i->l2i_assoc = assoc;
3309 l2i->l2i_ret = -1;
3310
3311 switch (x86_which_cacheinfo(cpi)) {
3312 case X86_VENDOR_Intel:
3313 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
3314 break;
3315 case X86_VENDOR_Cyrix:
3316 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
3317 break;
3318 case X86_VENDOR_AMD:
3319 amd_l2cacheinfo(cpi, l2i);
3320 break;
3321 default:
3322 break;
3323 }
3324 return (l2i->l2i_ret);
3325 }
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