What's your target more specifically? You mention 4ksd in commentary,
is it it?
This is the processor I'm running, it is a 32bit 96MHz MIPS 4ksd processor:
http://www.maximintegrated.com/datasheet/index.mvp/id/6134
It looks like n32 is for 64bit CPUs only, so I'm assuming I'm using o32.
Correct, n32 is option only for 64-bit processors, and o32 is the only
option for 32-bit processors.
As for 4ksd. It appears to be mips32r2 processor, and even with
SmartMIPS ASE. Actually on r2 compiler has all chances
to beat currently available assembler, if it recognizes rotates and
deploys rotate instruction. I have r2 code, and
wonder if you can test and benchmark it. SmartMIPS extension offers
improved support for bignum and polynomial
multiplication, but I have no code for it.
I can definitely test and benchmark whatever you want on the platform,
I'm definitely willing to try out any new code you may have.
The device is definitely a bit anemic from a performance standpoint,
How is it possible? The URL you mentioned above says "Industry's Highest
Performance, Most Secure 32-Bit MIPS Processor." :-) :-) :-)
SSL negotiation (where the device is the server) takes about 2s
as it currently stands, and that's with the current MIPS assembler
support in OpenSSL.
I was planning on running some actual benchmarks but hadn't gotten
around to it yet.
I've just made some commits and here is "workflow". First compile
linux-generic32 build [adding -march=4ksd] and collect output for
'openssl speed aes-128-cbc sha rsa1024' command. Then check-out latest
source [alternatively wait for *tomorrow* openssl-SNAP-20120916
snapshot], './Configure linux-mips32 -mips32r2', build and collect
output for above command. You can either post outputs here or send to me
personally. -mips32r2 engages r2 code in assembly modules, don't specify
your 4ksd at this point, we'll figure it out later. If your compiler
doesn't recognize -mips32r2, pass -D_MIPS_ARCH_MIPS32R2 to ./Configure.
Some notes on new Linux/MIPS config lines. I've chosen not to refer to
mips2-3-4, but to mips32 and mips64, which are current MIPS architecture
specifications. There also are mips32r2 and mips64r2 specifications. The
lines are endian-neutral in sense that they work on either endianness
target.
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