nova has worked hard over the last few cycles to identify and reduce
the amount of tech debt we're carrying. One such item identified early
on was the lack of automated testing and upstream documentation for NFV
features, such as CPU pinning, realtime, hugepages, SR-IOV, and PCI
passthrough. We discussed this at the Austin (M) summit and have been
slowly chugging away at it since through a combination of weekly SR-IOV 
meetings [1] and changes to the docs [2][3][4][5], code and in- [6] and
out-of-tree tests [7].

This work will continue for this cycle, however, we'd like to ask is
there any of these features where developers or operators can still
identify significant holes in either validation or (upstream)
documentation? If so, please give us a shout. This is something we'll
probably double back on in a PTG session, but we'd like to make full
use of the few months between now and then to really build on these
features.

I'd also like to take the opportunity to promote the weekly SR-IOV
meeting. We regularly address all things NFV at this meeting, so if
you've ideas on how to improve or build upon these features, this is as
good a place to bring said ideas up.

Cheers,
Stephen (sfinucan)

[1] http://eavesdrop.openstack.org/#SR-IOV/PCI_Passthrough_Meeting
[2] http://docs.openstack.org/networking-guide/config-sriov.html
[3] http://docs.openstack.org/admin-guide/compute-pci-passthrough.html
[4] http://docs.openstack.org/admin-guide/compute-cpu-topologies.html
[5] http://docs.openstack.org/admin-guide/compute-huge-pages.html
[6] https://github.com/openstack/nova/tree/master/nova/tests/functional
/libvirt
[7] https://github.com/openstack/intel-nfv-ci-tests

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