Joerg Albert írta: > Hi, > > On 04/06/2010 04:30 PM, Gabor Juhos wrote: > >> Nah, it was not "broken". The AR8216 driver was disabled by default because >> it >> is not usable on the AR913x based boards. The reason behind this is that you >> can't communicate with the switch via the MDIO bus, because its speed is too >> fast for the switch. > > Interesting. Does this imply that OpenWRT currently doesn't control the > AR8216, > i.e. the configuration from reset or bootloader is kept?
Yes, exactly. > Running OpenWRT svn r20534 on a Netgear WNR2000 says: > > Atheros AR9130 rev 1, CPU:400.000 MHz, AHB:200.000 MHz, DDR:400.000 MHz > > > In the bootloader I can see the PHY @ addr 0...4 (AFAIK integrated into the > AR8216): > > ar7100> mii info > PHY_PHYIDR2 @ 0x0 = 0xd042 > PHY_PHYIDR[1,2] @ 0x0 = 0x004dd042 > PHY 0x00: OUI = 0x1374, Model = 0x04, Rev = 0x02, 10baseT, HDX > PHY_PHYIDR2 @ 0x1 = 0xd042 > PHY_PHYIDR[1,2] @ 0x1 = 0x004dd042 > PHY 0x01: OUI = 0x1374, Model = 0x04, Rev = 0x02, 10baseT, HDX > PHY_PHYIDR2 @ 0x2 = 0xd042 > PHY_PHYIDR[1,2] @ 0x2 = 0x004dd042 > PHY 0x02: OUI = 0x1374, Model = 0x04, Rev = 0x02, 10baseT, HDX > PHY_PHYIDR2 @ 0x3 = 0xd042 > PHY_PHYIDR[1,2] @ 0x3 = 0x004dd042 > PHY 0x03: OUI = 0x1374, Model = 0x04, Rev = 0x02, 100baseT, FDX > PHY_PHYIDR2 @ 0x4 = 0xd042 > PHY_PHYIDR[1,2] @ 0x4 = 0x004dd042 > PHY 0x04: OUI = 0x1374, Model = 0x04, Rev = 0x02, 10baseT, HDX Yeah. The funny thing is that you can read the registers of PHY[01234] all the time, but the indirect access of the AR8216's internal registers don't work. > Is it just the switch core not able to cope with the high frequency on the > MDIO bus or > does the bootloader run the AHB at a lower speed? The bootloader lowers the speed of the AHB bus before it initializes the switch, and restore it after the initialization is done. > I guess the register AG71XX_REG_MII_CFG (drivers/net/ag71xx/ag71xx.h) > contains the divider for AHB clock => MDIO clock, set > in ag71xx_mdio.c::ag71xx_mdio_reset(). Is 28 (coded as 7) the highest > possible divider, i.e. only three bit for DIV? Yes. The datasheet says that at least. The problem is that you can't set it, because writing of the AG71XX_REG_MII_CFG register has no effect on the AR913x. >> The speed of the MDIO bus depends on the speed of the AHB bus. >> >> In theory it would be possible to decrease the speed of the AHB bus in the >> board >> init code, but that would affect the performance of the whole system. >> >> Another solution is to decrease the speed of the AHB bus before each MDIO bus >> access, and restore it after, but i don't know how it would affect other >> devices >> on the AHB bus. > > What is the highest MDIO and AHB frequency the AR8216 can work at? I don't know that exactly. IIRC, I saw it working with CPU=400MHz and AHB=100MHz on a board. >> To be precise, there is yet another solution: configuring the AR8216 switch >> with >> special ethernet packets. > > Is there any example source code for this (I guess headers != 0x10 80 are > needed)? You can find that in the u-boot's source code of the WNR2000 v1 for example. (u-boot-1.1.4/board/ar7100/common/athrs26_phy.c) > Does the same apply to the AR7240, whose built-in switch seems to be derived > from the AR8216? Nope. Regards, Gabor _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/mailman/listinfo/openwrt-devel
