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Hi everyone!
I started to port OpenWrt to the Rt3352F. I got a sample of each, Rt3352F,
Rt3052F and Rt3050 here to test.
The Rt3352F is a MIPS24Kc and therefore very similar to the Rt3052F. The main
differences are:
- the main CPU clock is @400MHz (compared to 384MHz on the Rt3052F)
- it got regular OHCI/EHCI USB instead of dwc_otg
I'm asking you to advise and comment on the work I did for now.
The clockrate cannot be identified from the CPUCLK register for all the chip
family, so I had to make another distinction based on SYSC_REG_CHIP_NAMEx
registers. It doesn't look very nice to have that in clock.c, so maybe I will
create a bunch of makros like RT3XXX_IS_RT3352F, RT3XXX_IS_RT3052F which returns
true if we got that cpu. I'm just not sure yet where would be the right place to
put those makros...
diff --git
a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
index 64918fe..e71537a 100644
- ---
a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
@@ -63,8 +63,8 @@
#define SYSTEM_CONFIG_CPUCLK_SHIFT 18
#define SYSTEM_CONFIG_CPUCLK_MASK 0x1
- -#define SYSTEM_CONFIG_CPUCLK_320 0x0
- -#define SYSTEM_CONFIG_CPUCLK_384 0x1
+#define SYSTEM_CONFIG_CPUCLK_LOW 0x0
+#define SYSTEM_CONFIG_CPUCLK_HIGH 0x1
#define SYSTEM_CONFIG_SRAM_CS0_MODE_SHIFT 2
#define SYSTEM_CONFIG_SRAM_CS0_MODE_MASK 0x3
#define SYSTEM_CONFIG_SRAM_CS0_MODE_NORMAL 0
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
index dff3738..177a839 100644
- --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
@@ -31,21 +31,33 @@ static struct clk rt305x_uart_clk;
void __init rt305x_clocks_init(void)
{
u32 t;
+ char n0, n1;
t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
+ n0 = (char) ((rt305x_sysc_rr(SYSC_REG_CHIP_NAME0) >> 24) & 0xff);
+ n1 = (char) ((rt305x_sysc_rr(SYSC_REG_CHIP_NAME1) >> 8) & 0xff);
+
switch (t) {
- - case SYSTEM_CONFIG_CPUCLK_320:
- - rt305x_cpu_clk.rate = 320000000;
+ case SYSTEM_CONFIG_CPUCLK_LOW:
+ if ( n0 == '3' && n1 == '2' ) // Rt3352F
+ rt305x_cpu_clk.rate = 400000000;
+ else // Rt3050, Rt3350
+ rt305x_cpu_clk.rate = 320000000;
break;
- - case SYSTEM_CONFIG_CPUCLK_384:
- - rt305x_cpu_clk.rate = 384000000;
+ case SYSTEM_CONFIG_CPUCLK_HIGH: // Rt3352F
+ rt305x_cpu_clk.rate = 384000000;
break;
}
rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
- - rt305x_uart_clk.rate = rt305x_sys_clk.rate;
+
+ if ( n0 == '3' && n1 == '2' ) // Rt3352F
+ rt305x_uart_clk.rate = rt305x_cpu_clk.rate / 10;
+ else // Rt3050, Rt3052F, Rt3350
+ rt305x_uart_clk.rate = rt305x_sys_clk.rate;
+
rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
}
The sample I got of the Rt3352F got 128MB of RAM, so I changed to maximum amount
of RAM, there doesn't seem to be a problem with the Rt3052F and Rt3050 sample I
got, but both of them got only 32MB. Someone who got any Rt30xx with 64MB (e.g.
fonera2.0n) should give this patch a try and see if the memory size is still
detected correctly:
diff --git
a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/ralink_soc.h
b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/ralink_soc.h
index c3206ec..6fad746 100644
- ---
a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/ralink_soc.h
+++
b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/ralink_soc.h
@@ -13,6 +13,6 @@
#define RALINK_SOC_SDRAM_BASE 0
#define RALINK_SOC_MEM_SIZE_MIN (2 * 1024 * 1024)
- -#define RALINK_SOC_MEM_SIZE_MAX (64 * 1024 * 1024)
+#define RALINK_SOC_MEM_SIZE_MAX (128 * 1024 * 1024)
#endif /* __RT288X_RALINK_SOC_H */
- From what I see in wive-ng (containing the RaLink SDK) and also DD-WRT
sources,
all needed for ohci/ehci usb to work is adding the platform resources. The main
question I got here is: where is this supposed to happen? I somehow got the
feeling that doing it in this way works, but it's not the right place:
http://svn.dd-wrt.com:8000/browser/src/linux/universal/linux-3.2/drivers/usb/host/ehci-rt3xxx.c
for two reasons:
- it relies in having asm/rt2880/rt_mmap.h which is part of RaLink SDK and
obsoleted by include/asm/mach-ralink/rt305x.h
- instead of having an additional include in the ehci driver, there should be
function in arch/mips/ralink/rt305x/devices.c to allocate and initialize the
ehci and ohci controller with only minor changes needed in the actual driver.
Looking forward to your comments!
Cheers
Daniel
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