* use chip select register to control chip select function instead of use chip select polarity * should support use gpio as cs pin * deselected the spi device when setup and add debug info
Signed-off-by: Michael Lee <[email protected]> --- ...0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch | 95 ++++++++++++++++------ 1 file changed, 68 insertions(+), 27 deletions(-) diff --git a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch b/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch index d1067ea..1b2476c 100644 --- a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch +++ b/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch @@ -25,7 +25,7 @@ obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o --- /dev/null +++ b/drivers/spi/spi-mt7621.c -@@ -0,0 +1,582 @@ +@@ -0,0 +1,623 @@ +/* + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver + * @@ -53,6 +53,7 @@ +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/swab.h> ++#include <linux/gpio.h> + +#include <ralink_regs.h> + @@ -208,30 +209,26 @@ + return (prescale << SPIMASTER_CLKSEL_OFFSET); +} + -+static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex) ++static void mt7621_spi_set_cs(struct spi_device *spi, bool enable) +{ -+ u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER); -+ -+ master |= 7 << 29; -+ master |= 1 << 2; -+ if (duplex) -+ master |= 1 << 10; -+ else -+ master &= ~(1 << 10); ++ struct mt7621_spi *rs = spidev_to_mt7621_spi(spi); ++ u32 reg; + -+ mt7621_spi_write(rs, MT7621_SPI_MASTER, master); -+} ++ if (spi->mode & SPI_CS_HIGH) ++ enable = !enable; ++ enable = !enable; + -+static void mt7621_spi_set_cs(struct spi_device *spi, int enable) -+{ -+ struct mt7621_spi *rs = spidev_to_mt7621_spi(spi); -+ int cs = spi->chip_select; -+ u32 polar = 0; ++ reg = mt7621_spi_read(rs, MT7621_SPI_MASTER); ++ reg &= ~(SPIMASTER_CS_MASK << SPIMASTER_CS_OFFSET); + -+ mt7621_spi_reset(rs, cs); + if (enable) -+ polar = BIT(cs); -+ mt7621_spi_write(rs, MT7621_SPI_POLAR, polar); ++ reg |= (spi->chip_select << SPIMASTER_CS_OFFSET); ++ else { ++ /* when disable just enable cs 8 instead */ ++ reg |= (SPIMASTER_CS_MASK << SPIMASTER_CS_OFFSET); ++ } ++ ++ mt7621_spi_write(rs, MT7621_SPI_MASTER, reg); +} + +static inline int mt7621_spi_wait_ready(struct mt7621_spi *rs, int len) @@ -247,6 +244,47 @@ + return -ETIMEDOUT; +} + ++static void mt7621_dump_reg(struct spi_master *master, const char *func) ++{ ++ struct mt7621_spi *rs = spi_master_get_devdata(master); ++ ++ dev_dbg(&master->dev, "%s trans: %08x, opcode: %08x, data0: %08x, " ++ "data1: %08x, data2: %08x, data3: %08x, " \ ++ "data4: %08x, data5: %08x, data6: %08x, " \ ++ "data7: %08x, master: %08x, morebuf: %08x, " \ ++ "qctl: %08x, status: %08x, polar: %08x, " \ ++ "space: %08x\n", ++ func, ++ mt7621_spi_read(rs, MT7621_SPI_TRANS), ++ mt7621_spi_read(rs, MT7621_SPI_OPCODE), ++ mt7621_spi_read(rs, MT7621_SPI_DATA0), ++ mt7621_spi_read(rs, MT7621_SPI_DATA0 + 4), ++ mt7621_spi_read(rs, MT7621_SPI_DATA0 + 8), ++ mt7621_spi_read(rs, MT7621_SPI_DATA0 + 12), ++ mt7621_spi_read(rs, MT7621_SPI_DATA0 + 16), ++ mt7621_spi_read(rs, MT7621_SPI_DATA0 + 20), ++ mt7621_spi_read(rs, MT7621_SPI_DATA0 + 24), ++ mt7621_spi_read(rs, MT7621_SPI_DATA0 + 28), ++ mt7621_spi_read(rs, MT7621_SPI_MASTER), ++ mt7621_spi_read(rs, MT7621_SPI_MOREBUF), ++ mt7621_spi_read(rs, MT7621_SPI_QUEUE_CTL), ++ mt7621_spi_read(rs, MT7621_SPI_STATUS), ++ mt7621_spi_read(rs, MT7621_SPI_POLAR), ++ mt7621_spi_read(rs, MT7621_SPI_SPACE)); ++} ++ ++/* copy from spi.c */ ++static void spi_set_cs(struct spi_device *spi, bool enable) ++{ ++ if (spi->mode & SPI_CS_HIGH) ++ enable = !enable; ++ ++ if (spi->cs_gpio >= 0) ++ gpio_set_value(spi->cs_gpio, !enable); ++ else if (spi->master->set_cs) ++ spi->master->set_cs(spi, !enable); ++} ++ +static int mt7621_spi_transfer_half_duplex(struct spi_master *master, + struct spi_message *m) +{ @@ -297,7 +335,7 @@ + val |= (rx_len * 8) << 12; + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val); + -+ mt7621_spi_set_cs(spi, 1); ++ spi_set_cs(spi, true); + + val = mt7621_spi_read(rs, MT7621_SPI_TRANS); + val |= SPITRANS_START; @@ -305,7 +343,7 @@ + + mt7621_spi_wait_ready(rs, 36); + -+ mt7621_spi_set_cs(spi, 0); ++ spi_set_cs(spi, false); + + for (i = 0; i < rx_len; i += 4) + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i); @@ -377,7 +415,7 @@ + val |= (rx_len * 8) << 12; + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val); + -+ mt7621_spi_set_cs(spi, 1); ++ spi_set_cs(spi, true); + + val = mt7621_spi_read(rs, MT7621_SPI_TRANS); + val |= SPITRANS_START; @@ -385,7 +423,7 @@ + + mt7621_spi_wait_ready(rs, 36); + -+ mt7621_spi_set_cs(spi, 0); ++ spi_set_cs(spi, false); + + for (i = 0; i < rx_len; i += 4) + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i); @@ -451,6 +489,11 @@ + /* enable more buffer mode */ + mt7621_spi_setbits(rs, MT7621_SPI_MASTER, SPIMASTER_MB_MODE); + ++ /* deselected the spi device */ ++ spi_set_cs(spi, false); ++ ++ mt7621_dump_reg(master, __func__); ++ + return 0; +} + @@ -547,8 +590,8 @@ + master->flags = SPI_MASTER_HALF_DUPLEX; + master->setup = mt7621_spi_setup; + master->prepare_message = mt7621_spi_prepare_message; ++ master->set_cs = mt7621_spi_set_cs; + master->transfer_one_message = mt7621_spi_transfer_one_message; -+ master->num_chipselect = 2; + + dev_set_drvdata(&pdev->dev, master); + @@ -559,8 +602,6 @@ + + device_reset(&pdev->dev); + -+ mt7621_spi_reset(rs, 0); -+ + ret = devm_spi_register_master(&pdev->dev, master); + if (ret < 0) { + dev_err(&pdev->dev, "devm_spi_register_master error.\n"); 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