Hi Ilya, OK with me!
BR, Jan > -----Original Message----- > From: Ilya Maximets <[email protected]> > Sent: Tuesday, 19 March, 2019 12:08 > To: [email protected]; Ian Stokes <[email protected]> > Cc: Kevin Traynor <[email protected]>; Ilya Maximets > <[email protected]>; Jan Scheurich <[email protected]> > Subject: [PATCH] dpif-netdev-perf: Fix millisecond stats precision with slower > TSC. > > Unlike x86 where TSC frequency usually matches with CPU frequency, another > architectures could have much slower TSCs. > For example, it's common for Arm SoCs to have 100 MHz TSC by default. > In this case perf module will check for end of current millisecond each 10K > cycles, i.e 10 times per millisecond. This could be not enough to collect > precise > statistics. > Fix that by taking current TSC frequency into account instead of hardcoding > the > number of cycles. > > CC: Jan Scheurich <[email protected]> > Fixes: 79f368756ce8 ("dpif-netdev: Detailed performance stats for PMDs") > Signed-off-by: Ilya Maximets <[email protected]> > --- > lib/dpif-netdev-perf.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/lib/dpif-netdev-perf.c b/lib/dpif-netdev-perf.c index > 52324858d..e7ed49e7e 100644 > --- a/lib/dpif-netdev-perf.c > +++ b/lib/dpif-netdev-perf.c > @@ -554,8 +554,8 @@ pmd_perf_end_iteration(struct pmd_perf_stats *s, int > rx_packets, > cum_ms = history_next(&s->milliseconds); > cum_ms->timestamp = now; > } > - /* Do the next check after 10K cycles (4 us at 2.5 GHz TSC clock). */ > - s->next_check_tsc = cycles_counter_update(s) + 10000; > + /* Do the next check after 4 us (10K cycles at 2.5 GHz TSC clock). */ > + s->next_check_tsc = cycles_counter_update(s) + get_tsc_hz() / > + 250000; > } > } > > -- > 2.17.1 _______________________________________________ dev mailing list [email protected] https://mail.openvswitch.org/mailman/listinfo/ovs-dev
