On 3/19/2019 1:01 PM, Jan Scheurich wrote:
Hi Ilya,
OK with me!
BR, Jan
-----Original Message-----
From: Ilya Maximets <[email protected]>
Sent: Tuesday, 19 March, 2019 12:08
To: [email protected]; Ian Stokes <[email protected]>
Cc: Kevin Traynor <[email protected]>; Ilya Maximets
<[email protected]>; Jan Scheurich <[email protected]>
Subject: [PATCH] dpif-netdev-perf: Fix millisecond stats precision with slower
TSC.
Unlike x86 where TSC frequency usually matches with CPU frequency, another
architectures could have much slower TSCs.
For example, it's common for Arm SoCs to have 100 MHz TSC by default.
In this case perf module will check for end of current millisecond each 10K
cycles, i.e 10 times per millisecond. This could be not enough to collect
precise
statistics.
Fix that by taking current TSC frequency into account instead of hardcoding the
number of cycles.
CC: Jan Scheurich <[email protected]>
Fixes: 79f368756ce8 ("dpif-netdev: Detailed performance stats for PMDs")
Signed-off-by: Ilya Maximets <[email protected]>
Thanks, applied to master, backported as far as 2.10.
Thanks
Ian
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