Hi, I would like to promote my project first., than I will ask you about porting OWFS.
I wrote Verilog RTL 1-wire master with the next features: - writen in Verilog HDL, tested on Altera Cyclone II FPGA - reset/presence and bit write/read timing implemented in hardware - byte access commands done in software (port of public domain kit 3.10) - power delivery option (functionality is a bit hardware dependent) - overdrive mode support (not tested yet) - integration into Altera SOPC builder and Nios II EDS The project it developed here: https://github.com/jeras/sockit_owm Its final destination will be here: http://opencores.org/project,sockit_owm It would be great if anybody would be willing to test, report bugs, or help in any other way. Regarding OWFS, I see two porting paths: 1. porting OWFS to Nios II EDS + uCOS (a small real time OS) 2. writing a Linux driver, running it on OpenRisc from OpenCores.org The first solution requires a minimalistic port of OWFS with only C API. It should fit into between 32KiB and 128KiB RAM+ROM. Is there a project with such a minimalistic port, so I could check it? Otherwise is there a clean way to do it? The Linux driver and OpenRisc port wil have to wait, I do not have the development environment ready yet. For now I stil have so me hardware tests to run and some documentation to write, but if there is an clean way to port OWFS it might be a better choice than the current port of the public domain kit. Regards, Iztok Jeras ------------------------------------------------------------------------------ Increase Visibility of Your 3D Game App & Earn a Chance To Win $500! Tap into the largest installed PC base & get more eyes on your game by optimizing for Intel(R) Graphics Technology. Get started today with the Intel(R) Software Partner Program. Five $500 cash prizes are up for grabs. http://p.sf.net/sfu/intelisp-dev2dev _______________________________________________ Owfs-developers mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/owfs-developers
