Ok, OWFS supports the bit-level interface.
Can you run OWFS on the CPU (nios II)?
We can run with a smaller C library (like ucLibc) and avoid all the
dubugging and fork/thread code.
You would need a working malloc

I need to do some tests to tell you the stripped down size.

I presume you'd write a C program that actually uses the data,
probably through the OWCAPI interface.

Is this what you have in mind?

Your alternative, the Public Domain Kit, is also a nice alternative.
It certainly is small and light weight. Digitemp might be another
option.

I guess I'm note sure what you eventually intend? A controller with
1-wire interface and your CPU running a control program?

On Fri, Nov 26, 2010 at 11:20 AM, Iztok Jeras <[email protected]> wrote:
> Thanks for your reply.
>
> I must firs state that this is not a commercial project, I do it for
> 'karma' (references), so I do not have a lot of time available.
>
> The simplest description would be, I need the parts of owfs that are
> equivalent to the public domain kit. But OWFS should be better mostly
> because it is newer and supports a wider range of 1-wire slaves.
>
> The easiest way for me to proceed would be to find an OWFS based
> project with the next properties:
> 1. a system with no or only a basic OS (malloc, scheduler) a
> micro-controller for example
> 2. a C API that can be used to access 1-wire devices like
> thermometers, memories, ... it should be possible to enable or disable
> a group of devices.
> 3. without a filesystem, network access
>
> The system inside a FPGA would look like this (from bottom to top):
> HARDWARE
> 1. sockit_owm as the 1-wire master
> 2. a system bus and interrupt line between the peripheral (sockit_owm)
> and the CPU (Nios II)
> 3. CPU Nios II, with some ROM (up to 2MB) and some RAM (form 128kB to 512kB)
> SOFTWARE:
> 4. low level access functions interacting directly with hardware
> registers, implementing only reset/presence detect write/read bit
> (there is no byte level support in hardware), overdrive and power
> supply options
> 5. a layer handling byte access, CRC, standard commands, ...
> 6. a C API layer handling device discovery, ...
> 7. a C API supporting thermometer ...
> 8. no filesystems, no network support
>
> There is nothing smart in my hardware, so it should not be restricted
> to a closed set of 1-wire slaves, since everything can be done in
> software.
>
> Without a micro-controller level port of OWFS I will probably stick
> with the public domain kit. Pointing me to low level functions that
> implement bit level transfers, byte access, CRC, device discovery,
> would also help.
>
> Regards,
> Iztok Jeras
>
> On Fri, Nov 26, 2010 at 4:18 PM, Paul Alfille <[email protected]> wrote:
>> Very interesting work.
>>
>> Regarding integration with OWFS, we need to clarify the scope.
>>
>> 1. Your device you be used as a bus master communicating with OWFS
>> running on another machine.
>>   OWFS would communicate with your device over whatever communication
>> means you implement (ethernet, serial, i2c, ...
>>   We've done this for a dozen prior devices, including
>> microprocessor-based designs. There are only a few 1-wire commands
>> that need to be supported.
>>
>> 2. Running owfs on the FPGA is a little trtickier. What would you
>> actually want to do? I assume your wouldn't have a user environment or
>> file system available.
>>
>> When you think about it, OWFS has 3 parts:
>> A. 1-wire communication to 1-wire slaves (via a bus master)
>> B. Knowledge about the specific slaves, and all the protocol details
>> needed  generate temperature and switch state and memory information
>> is a general way rather than low-level byte codes.
>> C. A communication method to the user -- filesystem, program calls,
>> web-page, network packets.
>> ( There is also some caching, locking, and optimizations built in, but
>> that's not essential ).
>>
>> Part B is the hard part, there are a lot of slaves. Most commercial
>> smart bus masters that do this only support a few of the slaves based
>> on commercial demand (temperature most commonly).
>>
>> I think the bus master is the easiest to implement. What is your vission?
>>
>> Paul Alfille
>>
>>
>> On Fri, Nov 26, 2010 at 5:21 AM, Iztok Jeras <[email protected]> wrote:
>>> Hi,
>>>
>>> I would like to promote my project first., than I will ask you about
>>> porting OWFS.
>>>
>>> I wrote Verilog RTL 1-wire master with the next features:
>>> - writen in Verilog HDL, tested on Altera Cyclone II FPGA
>>> - reset/presence and bit write/read timing implemented in hardware
>>> - byte access commands done in software (port of public domain kit 3.10)
>>> - power delivery option (functionality is a bit hardware dependent)
>>> - overdrive mode support (not tested yet)
>>> - integration into Altera SOPC builder and Nios II EDS
>>>
>>> The project it developed here:
>>> https://github.com/jeras/sockit_owm
>>> Its final destination will be here:
>>> http://opencores.org/project,sockit_owm
>>>
>>> It would be great if anybody would be willing to test, report bugs, or
>>> help in any other way.
>>>
>>>
>>> Regarding OWFS, I see two porting paths:
>>> 1. porting OWFS to Nios II EDS + uCOS (a small real time OS)
>>> 2. writing a Linux driver, running it on OpenRisc from OpenCores.org
>>>
>>> The first solution requires a minimalistic port of OWFS with only C
>>> API. It should fit into between 32KiB and 128KiB RAM+ROM. Is there a
>>> project with such a minimalistic port, so I could check it? Otherwise
>>> is there a clean way to do it?
>>>
>>> The Linux driver and OpenRisc port wil have to wait, I do not have the
>>> development environment ready yet.
>>>
>>>
>>> For now I stil have so me hardware tests to run and some documentation
>>> to write, but if there is an clean way to port OWFS it might be a
>>> better choice than the current port of the public domain kit.
>>>
>>> Regards,
>>> Iztok Jeras
>>>
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