Robert Herold <[EMAIL PROTECTED]> wrote:
> The loop version (size = 0x2c bytes, 8 passes thru loop, 2 memory write, 3
> memory reads)
>
> 10071E02: 4E560000 link a6,#0
> 10071E06: 2F05 move.l d5,-(sp)
> 10071E08: 1A2E0008 move.b 8(a6),d5
> 10071E0C: 7200 moveq #0,d1
> 10071E0E: 7400 moveq #0,d2
> 10071E10: 600E bra.s *+16 ; 0x10071e20
> 10071E12: D201 add.b d1,d1
> 10071E14: 1005 move.b d5,d0
> 10071E16: 02000001 andi.b #0x1,d0
> 10071E1A: 8200 or.b d0,d1
> 10071E1C: E20D lsr.b #1,d5
> 10071E1E: 5242 addq.w #1,d2
> 10071E20: 0C420008 cmpi.w #8,d2
> 10071E24: 6DEC blt.s *-18 ; 0x10071e12
> 10071E26: 1001 move.b d1,d0
> 10071E28: 2A1F move.l (sp)+,d5
> 10071E2A: 4E5E unlk a6
> 10071E2C: 4E75 rts
Here's where the in-line assembler pays off:
link a6,#0
move.l d3,-(sp)
move.b 8(a6),d1
moveq #0,d0
moveq #7,d3
1$ lsr.b d1
lsl.b d0
dbra.b d3,1$
move.l (sp)+,d3
unlk a6
rts
The lsr, lsl, and dbra instructions all fit into the instruction fetch
registers, and so once they fetched from memory the first time, the
remainder of the loop runs with NO memory cycles!
--
Roger Chaplin
<[EMAIL PROTECTED]>
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