>From: [EMAIL PROTECTED] >Date: Fri, 7 Feb 2003 00:05:55 EST > > >In a message dated 2/6/03 8:54:30 PM, [EMAIL PROTECTED] writes: > ><< >Must the video card be in PCI slot closest to processor, or at least a board >in that slot plus another driving the monitor in use. >>> > >Slot 1 and Slot 6 are the most popular, but there is no requirement that the >video card be in any particular slot.
However, video performance and the performance of any card which does large data transfers may be affected by slot placement. The summary is that there's a resource which improves performance and if one card grabs it another card may not be able to get it. The cards are initialized starting at slot 1 and working their way down to slot 6 (A1 - F2) so cards in slots 1 and 4 (A1, D2) are more likely to get the performance improving resource. This is (I think) why some folks have reported that the upper slot of each group of three gives better performance in some situations. The nitty gritty from Apple's "Designing PCI Cards and Drivers for Power Macintosh Computers" > Be advised that the SetProcessorCacheMode has an undocumented > limitation. The PowerPC address space is divided into sixteen 256-Mbyte > segments that are distinguished by the upper 4-bits of the effective address. > The SetProcessorCacheMode is only capable of changing the cache setting > for one contiguous section of memory per 256-Mbyte segment. Therefore, > if two PCI cards are configured where they both have PCI address > assignments in the same segment only one card can change its address > space cache setting. > For example, if two cards (card x and card y) have addresses mapped into > segment 8, one at 0x80800000 and another at 0x80801000, the first call to > SetProcessorCacheMode from the driver of card x to make a cacheable > address space in segment 8 will work. A second call, say from the driver of > card y, to modify the cache setting in segment 8 will not work nor will it > report an error. This scenario will most likely result in a lower than > expected performance for card y, because card y address space is actually > cache inhibited which disables PCI transactions of 32-byte cache lines. If > the two cards are mapped into different segments, such as 8 and A, then > they both can modify the cache settings within their perspective segments. > This limitation will be relaxed in the future. I seriously doubt that the last sentence ever came to be. That is they may have fixed it in later machines, but I suspect the original PCI Macs are stuck with this bug. I'm not a good enough programmer to know whether this is likely to be an OS limitation or a firmware (ROM) limitation, but my guess is that it's a ROM thing. I could be wrong though. Maybe later OSs fixed this issue. Some testing with various PCI cards and slot placements and OS versions would probably be revealing. Jeff Walther -- PCI-PowerMacs is sponsored by <http://lowendmac.com/> and... Small Dog Electronics http://www.smalldog.com | Refurbished Drives | -- Sonnet & PowerLogix Upgrades - start at $169 | & CDRWs on Sale! | Support Low End Mac <http://lowendmac.com/lists/support.html> PCI-PowerMacs list info: <http://lowendmac.com/lists/pci-powermacs.shtml> --> AOL users, remove "mailto:"; Send list messages to: <mailto:[EMAIL PROTECTED]> To unsubscribe, email: <mailto:[EMAIL PROTECTED]> For digest mode, email: <mailto:[EMAIL PROTECTED]> Subscription questions: <mailto:[EMAIL PROTECTED]> Archive:<http://www.mail-archive.com/pci-powermacs%40mail.maclaunch.com/> Using a Mac? Free email & more at Applelinks! http://www.applelinks.com
