On 25 Jan 2005 at 21:01, Kostas Kavoussanakis wrote: > According to folks in the list, not by much, as the silicon wafers for > this size have a great chance of yielding 0 (zero) usable sensor > chips. I understood it to be a hard, physical limitation.
I think you may have misread, yields for CCD/CMOS technologies are very good, the components in them are magnetudes in size larger than the current technologies. So any faults in the silicon have far less effect then on top there is the fact that errors are somewhat more tolerated in this type of technology. This is why we can all count our hot pixels. The cost of the vast area of silicon required for larger sensors is and will be the crux of the cost for some time. Rob Studdert HURSTVILLE AUSTRALIA Tel +61-2-9554-4110 UTC(GMT) +10 Hours [EMAIL PROTECTED] http://members.ozemail.com.au/~distudio/publications/ Pentax user since 1986, PDMLer since 1998
