Ian, Thanks for coming back.
The component with hidden pins came from an Orcad project, I think. The pins are assigned to the power nets in the component properties but have no net assigned on the PCB. If I make them visible they have no wire connection so I can't link them to the power rails. I could re-create the component but I would really like to get the schematics to inherit the nets from the PCB. The Navigator panel will take a bit of getting used to as I don't yet know what is right and what is wrong but one pointer to the bus problem is that each wire on the unconnected busses has two entries; one has a scope of 'local to document' and the other is 'sheet interface'. How do I convince DPX to actually connect these two together? DPX does not appear to have any documentation on resolving problems. When error messages come up there is nothing to indicate how to fix them. I would really like to know why the schematics can't be updated from the PCB Regards, Dave -----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Ian Wilson Sent: 18 October 2004 23:53 To: Protel EDA Discussion List Subject: Re: [PEDA] FW: A real DXP problem On 05:51 PM 18/10/2004, Dave Courtney said: >OK I'll try the old email address > >I have a multi-sheet hierarchical design using ports to link connections and >busses via the top level schematic. I then had some problems creating the >PCB. Some busses were not included on the layout and the hidden pins used on >some imported components did not have the power connections assigned. Dave, Hidden pins have changed in DXP. I am not completely sure of the extent of the changes - but in DXP you have the option of setting which hidden pins are connected to what net. Editing the pin allows you to change this. I am not sure if this is part of your problem at all. Can't tell without seeing the design. I hate hidden pins and never use them, so I have not delved into their behaviour in DXP/P2004 at all. If I ever use an Altium component I copy into my own library and unhide all the hidden pins and remove the duplicates power pins from all but one part. (To me a improvement would be to simply not support hidden pin connectivity at all - this would be a feature in my book. But I know others use the concept. I just think it is not worth the problems in this day of switched rails and multiple supply voltages.) As for the transfer of busses - there are limitations on busses in Protel products that have been there for ages and users have been asking for improvements. P2004 introduced bus joiners which allow you to collect dissimilar (non-bus) signals into a bus. **BUT** these only work in FPGA projects. Boy was I peeved when I found that out. Are your busses "Protel-correctly" formed? That is each nets is of the form BUS0, BUS1,... and the bus and ports labelled as BUS[0..15] (or whatever). There is a tutorial pdf on connectivity - not sure it may be targeting the different hierarchy modes though. > To >make some progress I edited the missing pins on the PCB. Now, when I use the >'Update schematics' option, the comparator find the differences but states >'no updates are possible to Flattened Project'. How should I resolve the >discrepancies between the schematics and PCB? Editing nets on the PCB is not what I would normally do but it should not itself cause a problem. The comparator should just spot the differences and offer to resolve them. If it is thinking that your manual edits added extra connections it should have just "offered" to remove them. The Navigator panel is a good place to investigate netlist issues. What you see when browsing the design with the Navigator should be what is transferred to the PCB. Have you checked your designs connectivity with the Navigator panel? If you are able to zip up and email your design to me I will have a quick look and see if I can spot anything obvious. Have you sent the design to Altium and asked for their advice? They offer to do that pretty regularly for posters on their forum. Ian ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[EMAIL PROTECTED] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search previous postings: http://www.mail-archive.com/[EMAIL PROTECTED] ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[EMAIL PROTECTED] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search previous postings: http://www.mail-archive.com/[EMAIL PROTECTED]
