Dennis,
I watched a few of them (6-8), yes I would have to admit they are
minimally instructive but I found them far from complete or fully instructive.
It is not much better than sitting and watching an experienced user operate the
package in real-time (as fast as they can go) while you are trying to learn.
Some of it just raised more questions than they answered. I went back and
checked for a pertinent example from what I viewed.
In the Smart Paste demo at approx. the 35-40% mark they are creating a
smart paste bus based upon the previously selected nets. I rewound and replayed
this section of the demo many times just trying to see what I might have missed
the first few times. They select "Ports, Wires and Netlabels" but from that
point forward there is no additional details that define a Bus, Wire, Port or a
Netlabel. Why it places a bus and doesn't place a set of wires or a Port. There
is also a port length setting as well as "Wire length", what determines that
you placed a Bus with the "Wire" length setting vs. a Port with the set "Port
length"? There was no choice or selection made to place a Bus, "Ports, Wires
and Netlabels", so if I had wanted individual Wires, a Port or Netlabels, I got
a Bus!
At about the 60% point of this same Smart Paste demo they add an input
port to a sheet, all that occurs on screen is that a bus and port symbol are
pasted next to a sheet symbol and then the cursor is clicked on the edge of the
sheet, magically a sheet input symbol with the correct symbol naming appears.
It is even already an input symbol with the correct name (how was it determined
that the symbol should be input and not output or bidirectional?). Maybe I am
missing something on this one because it seems it is part of the FPGA suite
function. Is it that advanced that it assumes your single click wants the input
port symbol, somehow based upon some previous input/output function elsewhere
on those signals? Do they have similar intelligence in regular SCH as well?
Although it could be rather annoying at times when the program is trying to
second guess your design intent. What happens with multiple outputs or inputs
tied together at some point, how would it determine your connection/signal-flow
intent in those cases? So here this is just one example where I have assumed
there were additional operations missing from the video.
Sincerely,
Brad Velander
Senior PCB Designer
Northern Airborne Technology
#14 - 1925 Kirschner Road,
Kelowna, BC, V1Y 4N7.
tel (250) 763-2329 ext. 225
fax (250) 762-3374
-----Original Message-----
From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
Sent: Wednesday, January 11, 2006 10:16 AM
To: Protel EDA Discussion List
Subject: Re: [PEDA] 6.0 ? it is here
i can't agree brad
i found the videos instructive, i didn't see any lags
and the stuff magically appearing i think is just good time saving editing
maybe they were using shortcuts so the panels wouldn't flood and cover
the screen, they're faster anyway
i couldn't figure how they did the new single layer viewing modes i saw,
so i went back to the video and yes although they did not 'show' it they
did vocalize the info i needed and i got it very quickly from that
they did say the defaults were something they were not and on the flip
view they showed an indication of the view direction on a menu icon
which i do not see, but i consider that to be very minor stuff
ds
_______________________________________________________________________
Integrated Controls, Inc. Tel: 415-647-0480 EXT 107
2851 21st Street Fax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com
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