Hi everyone, been studying Solaris' vm and x64 hat implementations and wanted to check if I understood this bit correctly.
On Sparc, a tlb miss leads to a hardware interruption which is picked up by the OS. On x64, a tlb miss doesn't cause an interrupt, but leads to a page fault in which case the processor will (snoop the correct address) and fix the missing entry. Did I get it right? thanks Rafael _______________________________________________ perf-discuss mailing list perf-discuss@opensolaris.org
