Basically correct. One clarification on terminology: a page fault refers to the software trap that allocates the physical page and creates the VA->PA translation. The scenario you describe on x86 where the translation already exists is not a page fault, it is a page table walk, in which the processor traverses the hierarchy of page tables stored in main memory to find the translation. If there is no translation at the proper slot in the table, then a #PF exception is generated (trap to the kernel).
Also, TLB miss handling has been improved on SPARC in the recently announced UltraSPARC T2 processor (fka Niagara 2). The UltraSPARC T2 supports "Hardware Tablewalk", in which the processor will directly load a translation from the TSB of cached translations stored in main memory, with no software trap required. The TSB is a single-level table, directly indexed by VA, and setup by software. See Chapter 12, Memory Management Unit, in the UltraSPARC T2 Programmers Reference Manual: http://opensparc-t2.sunsource.net/specs/UST2-UASuppl-current-draft-HP-EXT.pdf - Steve Sistare Rafael Vanoni wrote On 08/30/07 00:11,: > Hi everyone, > been studying Solaris' vm and x64 hat implementations and wanted to > check if I understood this bit correctly. > > On Sparc, a tlb miss leads to a hardware interruption which is picked up > by the OS. On x64, a tlb miss doesn't cause an interrupt, but leads to a > page fault in which case the processor will (snoop the correct address) > and fix the missing entry. > > Did I get it right? > > thanks > Rafael > _______________________________________________ > perf-discuss mailing list > perf-discuss@opensolaris.org _______________________________________________ perf-discuss mailing list perf-discuss@opensolaris.org
