Hello~
I have run the showevtinfo of perfmon2 on my Intel Q9550 machine which has
12MB L2 cache.
It shows that it could monitor two hardware events:
#-----------------------------
Name : L2_LINES_IN
Desc : L2 cache misses
Code : 0x24
Counters : [ 0 1 ]
Umask-00 : 0x40 : [SELF] : This core
Umask-01 : 0xc0 : [BOTH_CORES] : Both cores
Umask-02 : 0x30 : [ANY] : All inclusive
Umask-03 : 0x10 : [PREFETCH] : Hardware prefetch only
#-----------------------------
Name : LAST_LEVEL_CACHE_MISSES
Desc : count each cache miss condition for references to the last level
cache. The event count may include speculation, but excludes cache line
fills due to hardware prefetch. Alias to event L2_RQSTS:SEL
F_DEMAND_I_STATE
Code : 0x412e
Counters : [ 0 1 ]
#-----------------------------
In Q9550, the last level cache is L2 cache.
What is the difference between these two events?
Another question is, does the Umask-01 in L2_LINES_IN mask the both cores
which share the same 6MB L2 cache?
Any help would be grateful!
Dennis
------------------------------------------------------------------------------
Apps built with the Adobe(R) Flex(R) framework and Flex Builder(TM) are
powering Web 2.0 with engaging, cross-platform capabilities. Quickly and
easily build your RIAs with Flex Builder, the Eclipse(TM)based development
software that enables intelligent coding and step-through debugging.
Download the free 60 day trial. http://p.sf.net/sfu/www-adobe-com
_______________________________________________
perfmon2-devel mailing list
perfmon2-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
